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mb90911as/f912bs/v950amas f 2 mc-16lx mb90910 series 16-bit microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-04578 rev. *a revised april 12, 2016 the mb90910 series, loaded 1 channel full-can controller and fl ash rom, is general-purpose cypress 16-bit microcontroller designing for automotive and industrial applications. its main feature is the on-board can cont rollers, which conform to ver 2. 0 part a and part b, while supporting a very flexible message buffer scheme and so offering more functions than a normal full-can approach. with the new 0.18 ? ? m cmos technology, cypress now offers on-chip flash rom program memory up to 128 kbytes. the power supply (1.8 v) is supplied to the mcu core from an in ternal regulator circuit. this creates a major advantage in term s of emi and power consumption. the internal pll clock frequency multiplier provides an internal 31.25 ns instruction execution ti me from an external 4 mhz clo ck. the unit features a 4-channel input capture unit 1 channel 16-bit fr ee-run timer, 2-channel lin-uart, 1-channel uart, and 16-channel 8/10-bit a/d converter as the peripheral resource. features clock built-in pll clock frequency multiplication circuit selection of machine clocks (p ll clocks) is allowed among frequency division by 2 on oscillation clock and multiplication of 1 to 8 times of oscillation clock (for 4 mhz oscillation clock, 4 mhz to 32 mhz) minimum execution time of instruction : 31.25 ns (when operating with 4-mhz oscillation clock and 8-time multiplied pll clock) instruction system best suited to controller 16 mbytes cpu memory space 24-bit internal addressing wide choice of data types (bit, byte, word, and long word) wide choice of addressing modes (23 types) enhanced multiply-divide instructions with sign and reti instructions enhanced high-precision computing with 32-bit accumulator instruction system compatible with high-level language (c language) and multitask employing system stack pointer enhanced various pointer indirect instructions barrel shift instructions increased processing speed 4-byte instruction queue powerful interrupt function powerful 8-level, 34-cond ition interrupt feature up to 8 channels external interrupts are supported cpu-independent automatic data transfer func- tion expanded intelligent i/o service function (ei 2 os) : up to 16 channels low power consumption (standby) mode sleep mode (a mode that halts cpu operating clock) main timer mode (timebase time r mode that is transferred from main clock mode) pll timer mode (timebase timer mode that is transferred from pll clock mode) stop mode (a mode that stops oscillation clock) cpu blocking operation mode process cmos technology i/o port general purpose input/outp ut port (cmos output) : - 36 ports timer timebase timer, watchdog timer : 1 channel 8/16-bit ppg timer : 8-bit ? 6 channels or 16-bit ? 3 channels 16-bit reload timer : 2 channels 16- bit input/output timer ? -16-bit free-run timer : 1 channel (frt0 : icu 0/1/2/3) ? -16- bit input capture : (icu) : 4 channels full-can controller : 1 channel compliant with can specifications version 2.0 part a and b 16 message buffers are built in can wake-up function uart (lin/sci) : lin-uart ? 2 channels, uart ? 1 channel equipped with full-duplex double buffer clock-asynchronous or clock- synchronous serial trans- mission is available
document number: 002-04578 rev. *a page 2 of 64 mb90910 series dtp/external interrupt : up to 8 channels, can wakeup : up to 1 channel module for activation of expanded intelligent i/o service (ei 2 os) and generation of external interrupt by external input delay interrupt generator module generates interrupt request for task switching 8/10-bit a/d converter : 16 channels resolution is selectable between 8-bit and 10-bit activation by external trigger input is allowed conversion time : 3 ? s (at 24 mhz machine clock, including sampling time) program patch function address matching detection for 6 address pointers capable of changing input voltage for port automotive/cmos-schmitt input level (initial level is automotive in single-chip mode) rom security function the content of rom can be protected (only mask rom product). flash memory security function protects the content of flash memory
document number: 002-04578 rev. *a page 3 of 64 mb90910 series contents product lineup ................................................................ 4 pin assignment ................................................................ 6 pin description ................................................................. 7 i/o circuit type .............................................................. 10 handling devices ............................................................ 15 block diagrams .............................................................. 18 memory map .................................................................... 20 i/o map ............................................................................. 21 can controllers .............................................................. 29 interrupt factors, interrupt vectors, interrupt control register .............................................. 36 electrical characteristics ............................................... 38 absolute maximum ratings .... ................................... 38 recommended conditions ........................................ 40 dc characteristics .................................................... 41 ac characteristics ..................................................... 43 clock timing .............................................................. 43 reset standby input .................................................. 45 power-on reset ......................................................... 46 uart ......................................................................... 46 trigger input timing ........... ....................................... 51 timer related resource inpu t timing ....................... 52 timer related resource output timing .................... 52 can pll cycle jitter .............. .............. .............. ........ 53 a/d converter ............................................................ 54 definition of a/d converter terms ........................... 56 flash memory program/erase characteristics ......... 59 ordering information ..................................................... 60 package dimension ........................................................ 61 major changes .................................................................62
document number: 002-04578 rev. *a page 4 of 64 mb90910 series 1. product lineup (continued) part number parameter mb90v950amas mb90f912bs mb90911as type evaluation product flash memory product mask rom product cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier ( ? 1, ? 2, ? 3, ? 4, ? 6, ? 8, 1/2 when pll stops) minimum instruction execution ti me : 31.25 ns (4 mhz osc. pll ? 8) rom external 128 kbytes 64 kbytes ram 30 kbytes 8 kbytes 4 kbytes emulator-specific power supply* 1 yes ? fpga data* 2 rev 050617 ? adaptor board* 2 mb2147-20 rev.04c or later ? technology 0.35 ? m cmos with built-in power supply regulator 0.18 ? m cmos with built-in power supply regulator operation voltage range 5 v ? 10 ? 3.0 v to 5.5 v : when normal operating operating ambient tem- perature ? ? 40 c to ? 105 c package pga-299 lqfp-48 uart lin-uart ? 7 channels lin-uart ? 2 channels, uart ? 1 channel wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device (supported by lin-uart only) i 2 c (400 kbps) 2 channels ? a/d converter 24 input channels 16 input channels 10-bit or 8-bit resolution conversion time : min 3 ? s include sample time (per one channel) 16-bit reload timer 4 channels 2 channels operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys ? machine clock frequency) supports external event count function 16-bit i/o timer 2 channels 1 channel generates an interrupt signal on overflow operation clock fr eq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys ? machine clock freq.) i/o timer 0 (clock input frck0) co rresponds to icu0/1/2/3, ocu 0/1/2/3 i/o timer 1 (clock input frck1) co rresponds to icu4/5/6/7, ocu 4/5/6/7 16-bit output compare 8 channels ? generates an interrupt signal when one of the 16-bi t i/o timer matches the output compare register a pair of compare registers can be used to generate an output signal.
document number: 002-04578 rev. *a page 5 of 64 mb90910 series (continued) *1: it is setting of jumper switch (tool vcc) when emulator (mb2147-01) is used. please refer to the emulator hardware manual for the details. *2: contact the sales or support representative if using ot her than those above of fpga data and adaptor boards. part number parameter mb90v950amas mb90f912bs mb90911as 16-bit input capture 8 channels 4 channels rising edge, falling edge or risi ng & falling edge sensitive signals an interrupt upon external event 8/16-bit ppg 8 channels (16-bit) /16 channels (8-bit) sixteen 8-bit reload counters sixteen 8-bit reload registers for l pulse width sixteen 8 - bit reload registers for h pulse width 3 channels (16-bit) /6 channels (8-bit) six 8-bit reload counters six 8-bit reload registers for l pulse width six 8-bit reload registers for h pulse width supports 8-bit and 16-bit operation modes a pair of 8-bit reload counters can be conf igured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter operating clock fr eq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 ? s@fosc ? 4 mhz ( fsys ? machine clock frequency , fosc ? oscillation cl ock frequency ) can controller 3 channels 1 channel conforms to can specification version 2.0 part a and b automatic re-transmission in case of error automatic transmission in response to remote frames prioritized 16 message buffers for data and id?s supports multiple messages flexible configuration of acceptance filtering : full bit compare/full bit ma sk/two partial bit masks supports up to 1 mbps dtp/external interrupt (8 channels) can be used rising edge, falling edge, starting up by h/l level input, external interrupt, expanded intelligent i/o services (ei 2 os) d/a converter 8-bit ? 2 channels ? i/o ports virtually all external pins can be used as general purpose i/o port all ports are push-pull outputs bit-wise settable as input/output or peripheral signal can be configured 8 as cmos schmitt trigger / automotive inputs (i n blocks of 8 pins) ttl input level settable for external bus (32-pin only for external bus) flash memory (flash memory product only) supports automatic programming, embedded algorithm write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm boot block configuration erase can be performed on each block flash security
document number: 002-04578 rev. *a page 6 of 64 mb90910 series 2. pin assignment mb90f912bs, mb90911a s (top view) (fpt-48p-m26) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 35 34 36 48 47 46 45 44 43 42 41 40 39 38 37 p66/an6/ppgc(d) avss rst vcc vss c p40 p41 p82/sin0/int14r/tin2 p50/an8/sin2 avcc p44/frck0 p80/adtg/int12r p51/an9/sot2 x0 x1 p67/an7/ppge(f) avr p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5/ppga(b) p27/in3 p26/in2 p25/in1 p24/in0 p23/ppgf(e)* p22/ppgd(c)* p21/ppgb(a)* p20* md2 md1 md0 p52/an10/sck2 p53/an11/tin3 p54/an12/tot3/int8 p55/an13/int10 p56/an14/int11 p57/an15/int13 p84/sck0/int15r p83/sot0/tot2 p42/rx1/int9r p43/tx1 p86/sot1 p87/sck1 p85/sin1 lqfp-48 * : high current output port
document number: 002-04578 rev. *a page 7 of 64 mb90910 series 3. pin description (continued) pin no. pin name i/o circuit type* function 1av cc iv cc power input pin for analog circuit. 2 avr ? power (vref ? ) input pin for a/d converter. it should be below v cc . 3 to 7 p60 to p64 h general-purpose i/o port. an0 to an4 analog input pins for a/d converter. 8 to 10 p65 to p67 h general-purpose i/o port. an5 to an7 analog input pins for a/d converter. ppga (b) , ppgc (d) , ppge (f) output pins for ppg. 11 p80 f general-purpose i/o port. adtg trigger input pin for a/d converter. int12r external interrupt request input pin for int12r. 12 p50 l general-purpose i/o port. an8 analog input pin for a/d converter. sin2 serial data input pin for uart2. 13 p51 h general-purpose i/o port. an9 analog input pin for a/d converter. sot2 serial data output pin for uart2. 14 p52 h general-purpose i/o port. an10 analog input pin for a/d converter. sck2 clock i/o pin for uart2. 15 p53 h general-purpose i/o port. an11 analog input pin for a/d converter. tin3 event input pin for reload timer 3. 16 p54 h general-purpose i/o port. an12 analog input pin for a/d converter. tot3 output pin for reload timer 3 int8 external interrupt request input pin for int8. 17 p55 h general-purpose i/o port. an13 analog input pin for a/d converter. int10 external interrupt request input pin for int10.
document number: 002-04578 rev. *a page 8 of 64 mb90910 series (continued) pin no. pin name i/o circuit type* function 18 p56 h general-purpose i/o port (different i/o circuit type from mb90v950amas). an14 analog input pin for a/d converter. int11 external interrupt request input pin for int11. 19 p57 h general-purpose i/o port (different i/o circuit type from mb90v950amas). an15 analog input pin for a/d converter. int13 external interrupt request input pin for int13. 20 md2 d input pin for oper ation mode specification. 21, 22 md1, md0 c input pins for operation mode specification. 23 rst e reset input pin. 24 v cc ? power input pin (3.5 v to 5.5 v) . 25 v ss ? power input pin (0 v) . 26 c i power supply stabilization capacitor pi n. it should be connected to a higher than or equal to 0.1 ? f ceramic condenser. 27 x0 a oscillation input pin. 28 x1 oscillation output pin. 29 to 32 p27 to p24 g general-purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is en abled in single-chip mode. in3 to in0 event input pins for input capture 0 to 3. 33 to 35 p23 to p21 j general-purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is en abled in single-chip mode. high current output port (different i/o circuit type from mb90v950amas). ppgf (e) , ppgd (c) , ppgb(a) output pins for ppg. 36 p20 j general-purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is en abled in single-chip mode. high current output port (different i/o circuit type from mb90v950amas). 37 p85 k general-purpose i/o port. sin1 serial data input pin for uart1. 38 p87 f general-purpose i/o port. sck1 clock i/o pin for uart1. 39 p86 f general-purpose i/o port. sot1 serial data output pin for uart1.
document number: 002-04578 rev. *a page 9 of 64 mb90910 series (continued) * : for the i/o circ uit type, refer to ? i/o circuit type ?. pin no. pin name i/o circuit type* function 40 p43 f general-purpose i/o port. tx1 tx output pin for can1 controller. 41 p42 f general-purpose i/o port. rx1 rx input pin for can1 controller. int9r external interrupt request input pin for int9r. 42 p83 f general-purpose i/o port. sot0 serial data output pin for uart0. tot2 output pin for reload timer 2. 43 p84 f general-purpose i/o port. sck0 clock i/o pin for uart0. int15r external interrupt request input pin for int15r. 44 p82 k general-purpose i/o port. sin0 serial data input pin for uart0. int14r external interrupt request input pin for int14r. tin2 event input pin for reload timer 2. 45 p44 f general-purpose i/o port (different i/o circuit type from mb90v950amas). frck0 free-run timer 0 clock input pin. 46, 47 p40, p41 f general-purpose i/o port 48 av ss iv ss power input pin for analog circuit.
document number: 002-04578 rev. *a page 10 of 64 mb90910 series 4. i/o circuit type type circuit remarks a oscillation circuit : high-speed oscillation feedback resistor ? approx. 1 m ? (mask rom product, flash memory product) oscillation circuit : high-speed oscillation feedback resistor ? approx. 1 m ? (evaluation product) b unused c ? mask rom product / evaluation product : cmos hysteresis input pin ? flash memory product : cmos input pin d ? mask rom product / evaluation product : cmos hysteresis input pin ? flash memory product : - cmos input pin - no pull-down x1 x0 xout standby control signal x1 x0 standby control signal xout standby control signal x1a x0a xout r cmos hysteresis inputs r p u ll-down re s i s tor cmo s hy s tere s i s inp u t s
document number: 002-04578 rev. *a page 11 of 64 mb90910 series (continued) e cmos hysteresis input pin type circuit remarks r p u ll- u p re s i s tor cmo s hy s tere s i s inp u t s
document number: 002-04578 rev. *a page 12 of 64 mb90910 series (continued) type circuit remarks f ? cmos level output (i ol ? 4 ma, i oh ? ? 4 ma) ? cmos hysteresis inputs (v ih 0.8vcc v il 0.2vcc) (with the standby-time input shutdown func- tion) ? automotive input (with the standby-time input shutdown function) g ? cmos level output (i ol ? 4 ma, i oh ? ? 4 ma) ? cmos hysteresis inputs (v ih 0.8vcc v il 0.2vcc) (with the standby-time input shutdown func- tion) ? automotive input (with the standby-time input shutdown function) h ? cmos level output (i ol ? 4 ma, i oh ? ? 4 ma) ? cmos hysteresis inputs (v ih 0.8vcc v il 0.2vcc) (with the standby-time input shutdown func- tion) ? automotive input (with the standby-time input shutdown function) ? a/d analog input po u t no u t r cmo s hy s tere s i s inp u t s a u tomotive inp u t s s tandby control for inp u t s h u tdown p-ch n-ch r pull-up control pull-up resistor cmos hysteresis inputs automotive inputs pout nout standby control for input shutdown p-ch n-ch p-ch pout nout r cmos hysteresis inputs analog input automotive inputs standby control for input shutdown p-ch n-ch
document number: 002-04578 rev. *a page 13 of 64 mb90910 series (continued) type circuit remarks i protection circuit for power supply input j ? cmos level output (i ol ? 20 ma, i oh ? ? 14 ma) (mb90v950: i ol ? 4 ma, i oh ? ? 4 ma) ? cmos hysteresis inputs (v ih 0.8vcc v il 0.2vcc) (with the standby-time input shutdown func- tion) ? automotive input (with the standby-time input shutdown function) k ? cmos level output (i ol ? 4 ma, i oh ? ? 4 ma) ? cmos hysteresis input (v ih 0.7vcc v il 0.3vcc) (with standby-time input shutdown function) ? automotive input (with standby-time input shutdown function) ? cmos hysteresis inputs (v ih 0.8vcc v il 0.2vcc) (with the standby-time input shutdown func- tion) p-ch n-ch pout high current output nout high current output r pull-up control pull-up resistor cmos hysteresis inputs automotive inputs standby control for input shutdown p-ch n-ch p-ch pout nout r p-ch n-ch cmos hysteresis inputs automotive input standby control for input shutdown cmos hysteresis input
document number: 002-04578 rev. *a page 14 of 64 mb90910 series (continued) type circuit remarks l ? cmos level output (i ol = 4 ma, i oh = ? 4 ma) ? cmos hysteresis inputs (v ih 0.8vcc v il 0.2vcc) (with the standby-time input shutdown func- tion) ? automotive input (with the standby-time input shutdown func- tion) ? cmos hysteresis input (v ih 0.7vcc v il 0.3vcc) (with the standby-time input shutdown func- tion) ? a/d analog input pout nout r p-ch n-ch cmos hysteresis inputs automotive input standby control for input shutdown analog input cmos hysteresis input
document number: 002-04578 rev. *a page 15 of 64 mb90910 series 5. handling devices 1. preventing latch-up cmos ic chips may suffer latch-up under the following conditions : a voltage higher than v cc pin or lower than v ss pin is applied to an input or output pin. a voltage higher than the rated voltage is applied between v cc pin and v ss pin. the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current dras tically, causing thermal damage to the device. use meticulous care not to exceed the rating. for the same reason, also be careful not to let the analog power-supply voltage (av cc , avr) exceed the digital power-supply voltage. 2. treatment of unused pins leaving unused input pins open may result in permanent damage of the device due to misbehavior or latch-up. therefore, they mus t be pulled up or pulled down through resistors. in this case, those resistors should be more than 2 k ? . unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described c onnection. 3. using external clock the high-speed oscillator pins (x0, x1) can not be used for external clock inputs. 4. notes on during operation of pll clock mode on this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the pll clock mode is selected, a self-oscillator circuit contained in the pll ma y continue its operation at its self-running frequency. however, cypress will not guarantee results of operat ions if such failure occurs.
document number: 002-04578 rev. *a page 16 of 64 mb90910 series 5. power supply pins (v cc /v ss ) if there are multiple v cc and v ss pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent malfunction such as latch-up. to reduce unnecessary radiation, prevent ma lfunctioning of the strobe signal due to t he rise of ground level, and observe the s tandard for total output current, be sure to connect the v cc and v ss pins to the power supply and ground externally. connect v cc and v ss pins to the device from the current supply source at a low impedance. as a measure against power supply nois e, connect a capacitor of about 0.1 ? f as a bypass capacitor between v cc pin and v ss pin in the vicinity of v cc and v ss pins of the device. 6. pull-up/down resistors the mb90910 series does not support internal pull-up/down resist ors (port 2 : built-in pull-up resistors) . use external compon ents where needed. 7. crystal oscillator circuit noises around x0 or x1 pin may be possible causes of malfunctions. make sure to provide bypass capacitors via shortest distance from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, that lines of oscillation circuit do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board artw ork surrounding x0 and x1 pins with a ground area for stabilizi ng the operation. please ask the crystal maker to evaluate the o scillational characteristics of the crystal and this device. 8. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc and avr) and analog inputs (an0 to an15) after turning-on the digital power supply (v cc ) . turn-off the digital power after turning off the a/d converter power supply and analog inputs. in this case, make sure that the voltage does not exceed avrh or av cc . 9. connection of unused pins of a/d converter if a/d converter is not used connect unused pins of a/d converter to av cc ? v cc , av ss ? avr ? v ss . 10. notes on energization to prevent the internal regulator circuit from malfunction ing, set the voltage rise time during energization at 50 ? s or more (0.2 v to 2.7 v) . v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss mb90910 series
document number: 002-04578 rev. *a page 17 of 64 mb90910 series 11. stabilization of power supply voltage a sudden change in the power supply voltage may cause t he device to malfunction even within the specified v cc power supply voltage operating guarantee ra nge. therefore, the v cc power supply voltage should be stabilized. for reference, the power supply voltage should be controlled so that v cc ripple variations (peak-to-peak value) at commercial frequencies (50 hz/60 hz) fall below 10 ? of the standard v cc power supply voltage and the coeffici ent of transient fluctuation does not exceed 0.1 v/ms at instantaneous power switching. 12. initialization in the device, there are internal registers which are initialized only by a power-on reset. to initialize these registers, tur n on the power again. 13. notes on using can function to use can function, please set ?1? to direct bit of can direct mode register (cdmr) . if direct bit is set to ?0? (initial value) , wait states will be performed when accessing can registers. note : please refer to hardware manual of ?mb90910 series for detail of can direct mode register?. 14. flash security function the security bit is located in the area of the flash memory. if protection code 01 h is written in the security bi t, the flash memory is in the protected state by security. therefore, please do not write 01 h in this address if you do not use the security function. please refer to followin g table for the address of the security bit. 15. correspondence with t a ? ? 105 c or more if used exceeding t a ? ? 105 c, please consult with us due to the restricted reliability. it is ensured to write/erase data to the flash memory between t a ? ? 40 c and ? 105 c. flash memory size address for security bit mb90f912bs embedded 1 mbit flash memory fe0001 h
document number: 002-04578 rev. *a page 18 of 64 mb90910 series 6. block diagrams mb90v950amas ram 30 k b ytes lin-uart 7 ch a nnels dma sot6 to sot0 sck6 to sck0 sin6 to sin0 av cc av ss avrh avrl adtg da01, da00 ppgf to ppg0 sda1, sda0 scl1, scl0 frck0 in7 to in0 out7 to out0 frck1 rx2 to rx0 tx2 to tx0 tin3 to tin0 tot3 to tot0 ad15 to ad00 a23 to a16 ale rd wrl wrh hrq hak rdy clk int15 to int8 (int15r to int8r) int7 to int0 ckot an23 to an0 clock controller f 2 mc-16lx core 16- b it i/o timer 0 16- b it free-run timer 1 input c a pture 8 ch a nnels output comp a re 8 ch a nnels can controller 3 ch a nnels 16- b it relo a d timer 4 ch a nnels extern a l b us dtp/ extern a l interrupt clock monitor presc a ler (7 ch a nnels) 8/10- b it a/d converter 24 ch a nnels 8- b it d/a converter 2 ch a nnels intern a l d a t a b us 8/16- b it ppg 16 ch a nnels i 2 c interf a ce 2 ch a nnels x0, x1 rst
document number: 002-04578 rev. *a page 19 of 64 mb90910 series mb90f912bs, mb90911as ram ppgf(e), ppgd(c), ppgc(d), ppge(f) frck0 rx1 tx1 tin2, tin3 tot2, tot3 int8, int9r, int10, int11, int12r, int13, int14r, int15r x0, x1 rst adtg avr an15 to an0 av ss av cc sin0, sin1, sin2 sck0, sck1, sck2 in0 to in3 ppga(b), ppgb(a), sot0, sot1, sot2 *1 : only for mb90f912bs *2 : only for mb90911as clock controller f 2 mc-16lx core input capture 4 channels 16-bit i/o timer 0 can controller 1 channel 16 -bit reload timer 2 channels flash* 1 mask rom* 2 prescaler 3 channels lin-uart 2 channels uart 1 channel 8/10-bit a/d converter 16 channels 8/16-bit ppg 3 channels dtp/ external interrupt internal data bus
document number: 002-04578 rev. *a page 20 of 64 mb90910 series 7. memory map note : the high-order portion of bank 00 gives the image of the ff bank rom to make the small mode l of the c compiler effective . since the low-order 16 bits are the same, the table in rom c an be referred without using the far specification in the pointer declaration. for example, an attempt to access 00c000 h practically accesses the value at ffc000 h in rom. the rom area in bank ff exceeds 32 kbytes, a nd its entire image cannot be shown in bank 00. the image between ff8000 h and ffffff h is visible in bank 00, while the image between ff0000 h and ff7fff h is visible only in bank ff. ffffff h ff0000 h feffff h fe0000 h fdffff h fd0000 h fcffff h fc0000 h fbffff h fb0000 h faffff h fa0000 h f9ffff h 0000ef h 000000 h f90000 h f8ffff h f80000 h 00ffff h 007fff h 007900 h 0078ff h 000100 h 008000 h mb90v950amas ffffff h ff0000 h 0000ef h 000000 h 00ffff h 007fff h 007900 h 0020ff h 000100 h 008000 h mb90f912bs 010000 h feffff h 0000f0 h 0000ff h fe0000 h f70000 h f77fff h ffffff h ff0000 h 0000ef h 000000 h 00ffff h 007fff h 007900 h 0010ff h 000100 h 008000 h mb90911as 0000f0 h 0000ff h rom (ff bank) rom (fe bank) rom (fd bank) rom (fc bank) rom (fb bank) rom (fa bank) rom (f9 bank) rom (f8 bank) rom (ff bank) rom (image of ff bank) peripheral rom (image of ff bank) peripheral peripheral peripheral : not accessible ram 30 kbytes ram 8 kbytes external access area external access area rom (fe bank) rom (image of ff bank) peripheral peripheral ram4 kbytes rom (ff bank)
document number: 002-04578 rev. *a page 21 of 64 mb90910 series 8. i/o map (continued) address register abbrevia- tion access resource name initial value 000000 h ,00 0001 h reserved 000002 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 000003 h reserved 000004 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 000005 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 000006 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 000007 h reserved 000008 h port 8 data register pdr8 r/w port 8 xxxxxxxx b 000009 h ,00 000a h reserved 00000b h port 5 analog input enable register ader5 r/w port 5, a/d 11111111 b 00000c h port 6 analog input enable register ader6 r/w port 6, a/d 11111111 b 00000d h reserved 00000e h input level select register 0 ilsr0 r/w ports xxxxxxxx b 00000f h input level select register 1 ilsr1 r/w ports xxxx0xxx b 000010 h ,00 0011 h reserved 000012 h port 2 direction register ddr2 r/w port 2 00000000 b 000013 h reserved 000014 h port 4 direction register ddr4 r/w port 4 00000000 b 000015 h port 5 direction register ddr5 r/w port 5 00000000 b 000016 h port 6 direction register ddr6 r/w port 6 00000000 b 000017 h reserved 000018 h port 8 direction register ddr8 r/w port 8 00000000 b 000019 h reserved 00001a h port a direction register ddra w port a 00000111 b 00001b h to 00001d h reserved 00001e h port 2 pull-up control register pucr2 r/w port 2 00000000 b 00001f h reserved
document number: 002-04578 rev. *a page 22 of 64 mb90910 series (continued) address register abbrevia- tion access resource name initial value 000020 h serial mode register 0 smr0 w, r/w uart0 000000000 b 000021 h serial control register 0 scr0 w, r/w 00000000 b 000022 h reception/transmission data register 0 rdr0/tdr0 r/w 00000000 b / 111111111 b 000023 h serial status register 0 ssr0 r, r/w 00001000 b 000024 h extended communication control register 0 eccr0 r, w, r/w 000000xx b 000025 h extended status/control register 0 escr0 r/w 00000x00 b 000026 h baud rate generator register 00 bgr00 r/w, r 00000000 b 000027 h baud rate generator register 01 bgr01 r/w, r 00000000 b 000028 h serial mode register 1 smr1 w, r/w uart1 00000000 b 000029 h serial control register 1 scr1 w, r/w 00000000 b 00002a h reception/transmission data register 1 rdr1/tdr1 r/w 00000000 b / 11111111 b 00002b h serial status register 1 ssr1 r, r/w 00001000 b 00002c h extended communication control register 1 eccr1 r, w, r/w 000000xx b 00002d h extended status/control register 1 escr1 r/w 00000x00 b 00002e h baud rate generator register 10 bgr10 r/w, r 00000000 b 00002f h baud rate generator register 11 bgr11 r/w, r 00000000 b 000030 h to 00003a h reserved 00003b h address detect control register 1 pacsr1 r/w address match detection 1 11000000 b 00003c h to 000043 h reserved 000044 h ppga operation mode control register ppgca w, r/w 16-bit ppg a/b 01000111 b 000045 h ppgb operation mode control register ppgcb w, r/w 01000001 b 000046 h ppga/b count clock select register ppgab r/w 00000010 b 000047 h reserved 000048 h ppg c operation mode control register ppgcc w, r/w 16-bit ppg c/d 01000111 b 000049 h ppg d operation mode control register ppgcd w, r/w 01000001 b 00004a h ppg c/ppg d count clock select register ppgcd r/w 00000010 b 00004b h reserved
document number: 002-04578 rev. *a page 23 of 64 mb90910 series (continued) address register abbrevia- tion access resource name initial value 00004c h ppg e operation mode control register ppgce w, r/w 16-bit ppg e/f 01000111 b 00004d h ppg f operation mode control register ppgcf w, r/w 01000001 b 00004e h ppg e/ppg f count clock select register ppgef r/w 00000010 b 00004f h reserved 000050 h input capture control status 0/1 ics01 r/w input capture 0/1 00000000 b 000051 h input capture edge 0/1 ice01 r/w, r 111010xx b 000052 h input capture control status 2/3 ics23 r/w input capture 2/3 00000000 b 000053 h input capture edge 2/3 ice23 r 111111xx b 000054 h to 000063 h reserved 000064 h timer control status 2 tmcsr2 r/w 16-bit reload timer 2 00000000 b 000065 h timer control status 2 tmcsr2 r/w 11110000 b 000066 h timer control status 3 tmcsr3 r/w 16-bit reload timer 3 00000000 b 000067 h timer control status 3 tmcsr3 r/w 11110000 b 000068 h a/d control status 0 adcs0 r/w a/d converter 00011110 b 000069 h a/d control status 1 adcs1 r/w, w 00000001 b 00006a h a/d data 0 adcr0 r 00000000 b 00006b h a/d data 1 adcr1 r 11111100 b 00006c h a/d converter setting 0 adsr0 r/w 00000000 b 00006d h a/d converter setting 1 adsr1 r/w 00000000 b 00006e h reserved 00006f h rom mirror function select register romm w rom mirror 11111101 b 000070 h to 00007f h reserved 000080 h to 00008f h reserved for can controller 1. refer to ? can controllers ? 000090 h to 00009d h reserved 00009e h address detect control register 0 pacsr0 r/w address match detection 0 11000000 b
document number: 002-04578 rev. *a page 24 of 64 mb90910 series (continued) address register abbrevia- tion access resource name initial value 00009f h delayed interrupt/release register dirr r/w delayed interrupt generation module 11111110 b 0000a0 h low-power consumption mode control register lpmcr w, r/w low-power consumption control circuit 00011000 b 0000a1 h clock selection register ckscr r, r/w low-power consumption control circuit 11111100 b 0000a2 h to 0000a7 h reserved 0000a8 h watchdog timer control register wdtc r, w watchdog timer xxxxx111 b 0000a9 h timebase timer control register tbtc w, r/w timebase timer 11100100 b 0000aa h reserved 0000ab h to 0000ad h reserved 0000ae h flash memory control status register (flash devices only. otherwise reserved) fmcs r, r/w flash memory 000x0000 b 0000af h reserved 0000b0 h interrupt control register 00 icr00 w, r/w interrupt control 00000111 b 0000b1 h interrupt control register 01 icr01 w, r/w 00000111 b 0000b2 h interrupt control register 02 icr02 w, r/w 00000111 b 0000b3 h interrupt control register 03 icr03 w, r/w 00000111 b 0000b4 h interrupt control register 04 icr04 w, r/w 00000111 b 0000b5 h interrupt control register 05 icr05 w, r/w 00000111 b 0000b6 h interrupt control register 06 icr06 w, r/w 00000111 b 0000b7 h interrupt control register 07 icr07 w, r/w 00000111 b 0000b8 h interrupt control register 08 icr08 w, r/w 00000111 b 0000b9 h interrupt control register 09 icr09 w, r/w 00000111 b 0000ba h interrupt control register 10 icr10 w, r/w 00000111 b 0000bb h interrupt control register 11 icr11 w, r/w 00000111 b 0000bc h interrupt control register 12 icr12 w, r/w 00000111 b 0000bd h interrupt control register 13 icr13 w, r/w 00000111 b 0000be h interrupt control register 14 icr14 w, r/w 00000111 b 0000bf h interrupt control register 15 icr15 w, r/w 00000111 b 0000c0 h reserved
document number: 002-04578 rev. *a page 25 of 64 mb90910 series (continued) address register abbrevia- tion access resource name initial value 0000c1 h reserved 0000c2 h reserved 0000c3 h to 0000c9 h reserved 0000ca h external interrupt enable 1 enir1 r/w dtp/external interrupt 00000000 b 0000cb h external interrupt source 1 eirr1 r/w xxxxxxxx b 0000cc h detection level setting 1 elvr1 r/w 00000000 b 0000cd h 00000000 b 0000ce h external interrupt source select eissr r/w 00000000 b 0000cf h pll clock control register psccr w pll 11110000 b 0000d0 h to 0000d7 h reserved 0000d8 h serial mode register 2 smr2 w, r/w uart2 00000000 b 0000d9 h serial control register 2 scr2 w, r/w 00000000 b 0000da h reception/transmission data register 2 rdr2/ tdr2 r/w 00000000 b / 11111111 b 0000db h serial status register 2 ssr2 r, r/w 00001000 b 0000dc h extended communication control register 2 eccr2 r, w, r/w 000000xx b 0000dd h extended status/control register 2 escr2 r/w 00000x00 b 0000de h baud rate generator register 20 bgr20 r/w, r 00000000 b 0000df h baud rate generator register 21 bgr21 r/w, r 00000000 b 0000e0 h to 0000ff h reserved 007900 h to 007913 h reserved 007914 h reload register la prlla r/w 16-bit ppg a/b xxxxxxxx b 007915 h reload register ha prlha r/w xxxxxxxx b 007916 h reload register lb prllb r/w xxxxxxxx b 007917 h reload register hb prlhb r/w xxxxxxxx b 007918 h reload register lc prllc r/w 16-bit ppg c/d xxxxxxxx b 007919 h reload register hc prlhc r/w xxxxxxxx b 00791a h reload register ld prlld r/w xxxxxxxx b 00791b h reload register hd prlhd r/w xxxxxxxx b
document number: 002-04578 rev. *a page 26 of 64 mb90910 series (continued) address register abbrevia- tion access resource name initial value 00791c h reload register le prlle r/w 16-bit ppg e/f xxxxxxxx b 00791d h reload register he prlhe r/w xxxxxxxx b 00791e h reload register lf prllf r/w xxxxxxxx b 00791f h reload register hf prlhf r/w xxxxxxxx b 007920 h input capture register 0 ipcp0 r input capture 0/1* 00000000 b 007921 h input capture register 0 ipcp0 r 00000000 b 007922 h input capture register 1 ipcp1 r 00000000 b 007923 h input capture register 1 ipcp1 r 00000000 b 007924 h input capture register 2 ipcp2 r input capture 2/3* 00000000 b 007925 h input capture register 2 ipcp2 r 00000000 b 007926 h input capture register 3 ipcp3 r 00000000 b 007927 h input captureregister 3 ipcp3 r 00000000 b 007928 h to 00793f h reserved 007940 h timer data register 0 tcdt0 r/w i/o timer 0 00000000 b 007941 h timer data register 0 tcdt0 r/w 00000000 b 007942 h timer control status register 0 tccsl0 r/w 00000000 b 007943 h timer control status register 0 tccsh0 r/w 01100000 b 007944 h to 00794b h reserved 00794c h timer register 2/reload register 2 tmr2/tmrl r2 r/w 16-bit reload timer 2 xxxxxxxx b 00794d h r/w xxxxxxxx b 00794e h timer register 3/reload register 3 tmr3/tmrl r3 r/w 16-bit reload timer 3 xxxxxxxx b 00794f h r/w xxxxxxxx b 007950 h to 00795f h reserved 007960 h reserved 007961 h to 00796d h reserved 00796e h can direct mode register (mb90v950amas only) cdmr r/w can clock sync 11111110 b 00796f h to 0079a1 h reserved
document number: 002-04578 rev. *a page 27 of 64 mb90910 series (continued) address register abbrevia- tion access resource name initial value 0079a2 h flash write control register 0 fwr0 r/w flash 00000000 b 0079a3 h flash write control register 1 fwr1 r/w 00000000 b 0079a4 h to 0079b1 h reserved 0079b2 h reserved 0079b3 h to 0079b7 h reserved 0079b8 h reserved 0079b9 h reserved 0079ba h reserved 0079bb h reserved 0079bc h reserved 0079bd h reserved 0079be h reserved 0079bf h reserved 0079c0 h to 0079df h reserved 0079e0 h detect address setting register 0 padr0 r/w address match detection 0 xxxxxxxx b 0079e1 h detect address setting register 0 padr0 r/w xxxxxxxx b 0079e2 h detect address setting register 0 padr0 r/w xxxxxxxx b 0079e3 h detect address setting register 1 padr1 r/w xxxxxxxx b 0079e4 h detect address setting register 1 padr1 r/w xxxxxxxx b 0079e5 h detect address setting register 1 padr1 r/w xxxxxxxx b 0079e6 h detect address setting register 2 padr2 r/w xxxxxxxx b 0079e7 h detect address setting register 2 padr2 r/w xxxxxxxx b 0079e8 h detect address setting register 2 padr2 r/w xxxxxxxx b 0079e9 h to 0079ef h reserved
document number: 002-04578 rev. *a page 28 of 64 mb90910 series (continued) * : the initial value of mb90v950amas is xxxxxxxx b . notes : ? initial value of ?x? represents undefined value. ? do not write to reserved address in i/o map. a r ead access to reserved addresses results in reading ?x?. address register abbrevia- tion access resource name initial value 0079f0 h detect address setting register 3 padr3 r/w address match detection 1 xxxxxxxx b 0079f1 h detect address setting register 3 padr3 r/w xxxxxxxx b 0079f2 h detect address setting register 3 padr3 r/w xxxxxxxx b 0079f3 h detect address setting register 4 padr4 r/w xxxxxxxx b 0079f4 h detect address setting register 4 padr4 r/w xxxxxxxx b 0079f5 h detect address setting register 4 padr4 r/w xxxxxxxx b 0079f6 h detect address setting register 5 padr5 r/w xxxxxxxx b 0079f7 h detect address setting register 5 padr5 r/w xxxxxxxx b 0079f8 h detect address setting register 5 padr5 r/w xxxxxxxx b 0079f9 h to 007bff h reserved 007c00 h to 007cff h reserved for can controller. refer to ? can controllers ? 007d00 h to 007dff h reserved for can controller. refer to ? can controllers ? 007e00 h to 007fff h reserved
document number: 002-04578 rev. *a page 29 of 64 mb90910 series 9. can controllers conforms to can specificatio n ver 2.0 part a and part b ? supports transmission/reception in st andard frame and extended frame formats supports transmitting of data frames by receiving remote frames 16 transmitting/receiving message buffers ? 29-bit id and 8-byte data ? multi-level message buffer configuration provides full-bit comparison, full-bit mask , acceptance register 0/acceptance regist er 1 for each message buffer as id acceptan ce mask ? 2 acceptance mask registers in either standard frame format or extended frame formats bit rate programmable from 10 kbps/s to 1 mbps/s (when input clock is at 16 mhz) list of control registers (1) address register abbreviation access initial value can1 000080 h message buffer valid register bvalr r/w 00000000 00000000 b 000081 h 000082 h transmit request register treqr r/w 00000000 00000000 b 000083 h 000084 h transmit cancel register tcanr w 00000000 00000000 b 000085 h 000086 h transmission complete register tcr r/w 00000000 00000000 b 000087 h 000088 h receive complete register rcr r/w 00000000 00000000 b 000089 h 00008a h remote request receiving register rrtrr r/w 00000000 00000000 b 00008b h 00008c h receive overrun register rovrr r/w 00000000 00000000 b 00008d h 00008e h reception interrupt enable register rier r/w 00000000 00000000 b 00008f h
document number: 002-04578 rev. *a page 30 of 64 mb90910 series list of control registers (2) address register abbreviation access initial value can1 007d00 h control status register csr r/w, w r/w, r 0xxxx0x1 00xxx000 b 007d01 h 007d02 h last event indicator register leir r/w 000x0000 xxxxxxxx b 007d03 h 007d04 h receive and transmit error counter rtec r 00000000 00000000 b 007d05 h 007d06 h bit timing register btr r/w 11111111 x1111111 b 007d07 h 007d08 h ide register ider r/w xxxxxxxx xxxxxxxx b 007d09 h 007d0a h transmit rtr register trtrr r/w 00000000 00000000 b 007d0b h 007d0c h remote frame receive waiting register rfwtr r/w xxxxxxxx xxxxxxxx b 007d0d h 007d0e h transmit interrupt enable register tier r/w 00000000 00000000 b 007d0f h 007d10 h acceptance mask select register amsr r/w xxxxxxxx xxxxxxxx b 007d11 h 007d12 h xxxxxxxx xxxxxxxx b 007d13 h 007d14 h acceptance mask register 0 amr0 r/w xxxxxxxx xxxxxxxx b 007d15 h 007d16 h xxxxxxxx xxxxxxxx b 007d17 h 007d18 h acceptance mask register 1 amr1 r/w xxxxxxxx xxxxxxxx b 007d19 h 007d1a h xxxxxxxx xxxxxxxx b 007d1b h
document number: 002-04578 rev. *a page 31 of 64 mb90910 series list of message buffers (id registers) (continued) address register abbreviation access initial value can1 007c00 h to 007c1f h general-purpose ram ? r/w xxxxxxxx b to xxxxxxxx b 007c20 h id register 0 idr0 r/w xxxxxxxx xxxxxxxx b 007c21 h 007c22 h xxxxxxxx xxxxxxxx b 007c23 h 007c24 h id register 1 idr1 r/w xxxxxxxx xxxxxxxx b 007c25 h 007c26 h xxxxxxxx xxxxxxxx b 007c27 h 007c28 h id register 2 idr2 r/w xxxxxxxx xxxxxxxx b 007c29 h 007c2a h xxxxxxxx xxxxxxxx b 007c2b h 007c2c h id register 3 idr3 r/w xxxxxxxx xxxxxxxx b 007c2d h 007c2e h xxxxxxxx xxxxxxxx b 007c2f h 007c30 h id register 4 idr4 r/w xxxxxxxx xxxxxxxx b 007c31 h 007c32 h xxxxxxxx xxxxxxxx b 007c33 h 007c34 h id register 5 idr5 r/w xxxxxxxx xxxxxxxx b 007c35 h 007c36 h xxxxxxxx xxxxxxxx b 007c37 h 007c38 h id register 6 idr6 r/w xxxxxxxx xxxxxxxx b 007c39 h 007c3a h xxxxxxxx xxxxxxxx b 007c3b h 007c3c h id register 7 idr7 r/w xxxxxxxx xxxxxxxx b 007c3d h 007c3e h xxxxxxxx xxxxxxxx b 007c3f h
document number: 002-04578 rev. *a page 32 of 64 mb90910 series (continued) address register abbreviation access initial value can1 007c40 h id register 8 idr8 r/w xxxxxxxx xxxxxxxx b 007c41 h 007c42 h xxxxxxxx xxxxxxxx b 007c43 h 007c44 h id register 9 idr9 r/w xxxxxxxx xxxxxxxx b 007c45 h 007c46 h xxxxxxxx xxxxxxxx b 007c47 h 007c48 h id register 10 idr10 r/w xxxxxxxx xxxxxxxx b 007c49 h 007c4a h xxxxxxxx xxxxxxxx b 007c4b h 007c4c h id register 11 idr11 r/w xxxxxxxx xxxxxxxx b 007c4d h 007c4e h xxxxxxxx xxxxxxxx b 007c4f h 007c50 h id register 12 idr12 r/w xxxxxxxx xxxxxxxx b 007c51 h 007c52 h xxxxxxxx xxxxxxxx b 007c53 h 007c54 h id register 13 idr13 r/w xxxxxxxx xxxxxxxx b 007c55 h 007c56 h xxxxxxxx xxxxxxxx b 007c57 h 007c58 h id register 14 idr14 r/w xxxxxxxx xxxxxxxx b 007c59 h 007c5a h xxxxxxxx xxxxxxxx b 007c5b h 007c5c h id register 15 idr15 r/w xxxxxxxx xxxxxxxx b 007c5d h 007c5e h xxxxxxxx xxxxxxxx b 007c5f h
document number: 002-04578 rev. *a page 33 of 64 mb90910 series list of message buffers (dlc registers and data registers) (continued) address register abbreviation access initial value can1 007c60 h dlc register 0 dlcr0 r/w xxxxxxxx b 007c61 h 007c62 h dlc register 1 dlcr1 r/w xxxxxxxx b 007c63 h 007c64 h dlc register 2 dlcr2 r/w xxxxxxxx b 007c65 h 007c66 h dlc register 3 dlcr3 r/w xxxxxxxx b 007c67 h 007c68 h dlc register 4 dlcr4 r/w xxxxxxxx b 007c69 h 007c6a h dlc register 5 dlcr5 r/w xxxxxxxx b 007c6b h 007c6c h dlc register 6 dlcr6 r/w xxxxxxxx b 007c6d h 007c6e h dlc register 7 dlcr7 r/w xxxxxxxx b 007c6f h 007c70 h dlc register 8 dlcr8 r/w xxxxxxxx b 007c71 h 007c72 h dlc register 9 dlcr9 r/w xxxxxxxx b 007c73 h 007c74 h dlc register 10 dlcr10 r/w xxxxxxxx b 007c75 h 007c76 h dlc register 11 dlcr11 r/w xxxxxxxx b 007c77 h 007c78 h dlc register 12 dlcr12 r/w xxxxxxxx b 007c79 h 007c7a h dlc register 13 dlcr13 r/w xxxxxxxx b 007c7b h 007c7c h dlc register 14 dlcr14 r/w xxxxxxxx b 007c7d h 007c7e h dlc register 15 dlcr15 r/w xxxxxxxx b 007c7f h
document number: 002-04578 rev. *a page 34 of 64 mb90910 series (continued) address register abbreviation access initial value can1 007c80 h to 007c87 h data register 0 (8 bytes) dtr0 r/w xxxxxxxx b to xxxxxxxx b 007c88 h to 007c8f h data register 1 (8 bytes) dtr1 r/w xxxxxxxx b to xxxxxxxx b 007c90 h to 007c97 h data register 2 (8 bytes) dtr2 r/w xxxxxxxx b to xxxxxxxx b 007c98 h to 007c9f h data register 3 (8 bytes) dtr3 r/w xxxxxxxx b to xxxxxxxx b 007ca0 h to 007ca7 h data register 4 (8 bytes) dtr4 r/w xxxxxxxx b to xxxxxxxx b 007ca8 h to 007caf h data register 5 (8 bytes) dtr5 r/w xxxxxxxx b to xxxxxxxx b 007cb0 h to 007cb7 h data register 6 (8 bytes) dtr6 r/w xxxxxxxx b to xxxxxxxx b 007cb8 h to 007cbf h data register 7 (8 bytes) dtr7 r/w xxxxxxxx b to xxxxxxxx b 007cc0 h to 007cc7 h data register 8 (8 bytes) dtr8 r/w xxxxxxxx b to xxxxxxxx b 007cc8 h to 007ccf h data register 9 (8 bytes) dtr9 r/w xxxxxxxx b to xxxxxxxx b 007cd0 h to 007cd7 h data register 10 (8 bytes) dtr10 r/w xxxxxxxx b to xxxxxxxx b 007cd8 h to 007cdf h data register 11 (8 bytes) dtr11 r/w xxxxxxxx b to xxxxxxxx b 007ce0 h to 007ce7 h data register 12 (8 bytes) dtr12 r/w xxxxxxxx b to xxxxxxxx b 007ce8 h to 007cef h data register 13 (8 bytes) dtr13 r/w xxxxxxxx b to xxxxxxxx b
document number: 002-04578 rev. *a page 35 of 64 mb90910 series (continued) address register abbreviation access initial value can1 007cf0 h to 007cf7 h data register 14 (8 bytes) dtr14 r/w xxxxxxxx b to xxxxxxxx b 007cf8 h to 007cff h data register 15 (8 bytes) dtr15 r/w xxxxxxxx b to xxxxxxxx b
document number: 002-04578 rev. *a page 36 of 64 mb90910 series 10. interrupt factors, interrupt vectors, in terrupt control register (continued) interrupt cause ei 2 os corresponding interrupt vector interrupt control register number address number address reset n #08 ffffdc h ?? int9 instruction n #09 ffffd8 h ?? exception n #10 ffffd4 h ?? reserved n #11 ffffd0 h icr00 0000b0 h reserved n #12 ffffcc h can 1 reception n #13 ffffc8 h icr01 0000b1 h can 1 transmission/node status n #14 ffffc4 h reserved n #15 ffffc0 h icr02 0000b2 h reserved n #16 ffffbc h reserved n #17 ffffb8 h icr03 0000b3 h reserved n #18 ffffb4 h 16-bit reload timer 2 y1 #19 ffffb0 h icr04 0000b4 h 16-bit reload timer 3 y1 #20 ffffac h reserved n #21 ffffa8 h icr05 0000b5 h reserved n #22 ffffa4 h ppg c/d n #23 ffffa0 h icr06 0000b6 h ppg a/b/e/f n #24 ffff9c h timebase timer n #25 ffff98 h icr07 0000b7 h external interrupt 8 to 11 y1 #26 ffff94 h reserved n #27 ffff90 h icr08 0000b8 h external interrupt 12 to 15 y1 #28 ffff8c h a/d converter y1 #29 ffff88 h icr09 0000b9 h i/o timer 0 n #30 ffff84 h reserved n #31 ffff80 h icr10 0000ba h reserved n #32 ffff7c h input capture 0 to 3 y1 #33 ffff78 h icr11 0000bb h reserved n #34 ffff74 h uart 0 reception y2 #35 ffff70 h icr12 0000bc h uart 0 transmission y1 #36 ffff6c h uart 1 reception y2 #37 ffff68 h icr13 0000bd h uart 1 transmission y1 #38 ffff64 h
document number: 002-04578 rev. *a page 37 of 64 mb90910 series (continued) y1 : usable y2 : usable, with ei 2 os stop function n : unusable notes : ? the peripheral resources sharing the icr register have the same interrupt level. ? when the peripheral resources sharing the icr register use extended intelligent i/o service, only one can use extended intelligent i/o service at a time. ? when either of the 2 peripheral resources sharing the icr register specifie s extended intelligent i/o service, the other one cannot use interrupts. interrupt cause ei 2 os corresponding interrupt vector interrupt control register number address number address uart 2 reception y2 #39 ffff60 h icr14 0000be h uart 2 transmission y1 #40 ffff5c h flash memory n #41 ffff58 h icr15 0000bf h delayed interrupt generation module n #42 ffff54 h
document number: 002-04578 rev. *a page 38 of 64 mb90910 series 11. electrical characteristics 11.1 absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss ? 6.0 v av cc v ss ? 0.3 v ss ? 6.0 v v cc ? av cc * 2 avr v ss ? 0.3 v ss ? 6.0 v av cc avr* 2 input voltage* 1 v i v ss ? 0.3 v ss ? 6.0 v *3 output voltage* 1 v o v ss ? 0.3 v ss ? 6.0 v *3 maximum clamp current i clamp ? 2.0 ? 2.0 ma *6 total maximum clamp current ? |i clamp | ? 40 ma *6 ?l? level maximum output current i ol1 ? 15 ma *4 i ol2 ? 40 ma *5 ?l? level average output current i olav1 ? 4ma*4 i olav2 ? 30 ma *5 ?l? level maximum overall output current ? i ol1 ? 125 ma *4 ? i ol2 ? 160 ma *5 ?l? level average overall output current ? i olav1 ? 40 ma *4 ? 105 c ? t a ? ? 125 c ? i olav2 *5 ? 105 c ? t a ? ? 125 c ? i olav1 ? 40 ma *4 ? 40 c ? t a ? ? 105 c ? i olav2 *5 ? 40 c ? t a ? ? 105 c ?h? level maximum output current i oh1 ? ? 15 ma *4 i oh2 ? ? 40 ma *5 ?h? level average output current i ohav1 ? ? 4ma*4 i ohav2 ? ? 30 ma *5 ?h? level maximum overall output current ? i oh1 ? ? 125 ma *4 ? i oh2 ? ? 160 ma *5 ?h? level average overall output current ? i ohav1 ? ? 40 ma *4 ? 105 c ? t a ? ? 125 c ? i ohav2 *5 ? 105 c ? t a ? ? 125 c ? i ohav1 ? ? 40 ma *4 ? 40 c ? t a ? ? 105 c ? i ohav2 *5 ? 40 c ? t a ? ? 105 c power consumption p d ? 420 mw operating temperature t a ? 40 ? 105 c ? 40 ? 125 c *7 storage temperature t stg ? 55 ? 150 c
document number: 002-04578 rev. *a page 39 of 64 mb90910 series (continued) *1 : this parameter is based on v ss ? av ss ? 0 v. *2 : set av cc and v cc to the same voltage. make sure that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. *3 : v i and v o should not exceed v cc ? 0.3 v. v i should not exceed the specified ratings. however, if the maximum current to/from an input is limited by so me means with external components, the i clamp rating supersedes the v i rating. *4 : applicable to pins : p24 to p27, p40 to p44, p50 to p57, p60 to p67, p80, p82 to p87 *5 : applicable to pins : p20 to p23 * 6 : applicable to pins : p20 to p27, p40 to p44, p50 to p55, p57, p60 to p67, p80, p82 to p87 ? use within recommended operating conditions. ? use at dc voltage (current) . ? the ? b signal should always be applied a connecting limit resistance between the ? b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the ? b signal is applied the input current to the microcontroller pin does not exceed rated values , either instantaneously or for prolonged periods. ? note that when the microcontrolle r drive current is low, such as in the power saving modes, the ? b input potential may pass through the protective di ode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a ? b signal is inputted when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the ? b input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the ? b input pin open. ? recommended circuit sample : *7 : if used exceeding t a ? ? 105 c, please consult with us due to the restricted reliability. it is ensured to write/erase da ta to the flash memory between t a ? ? 40 c and ? 105 c. warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuits ? b input (0 v to 16 v) limiting resistance protective diode
document number: 002-04578 rev. *a page 40 of 64 mb90910 series 11.2 recommended conditions (v ss ? av ss ? 0 v) * : for the restricted reliability, contact us if use the devices over ta=+105 c. it is ensured to write/erase data to the flash memory between t a ? ? 40 c and ? 105 c. warning: the recommended operating conditions are requi red in order to ensure t he normal operation of the semiconductor device. all of the device's elec trical characteristics are warranted when the device is operated within these ranges. always use semiconductor devi ces within their recommended operating condition ranges. operation outside these ranges may adversely affe ct reliability and could result in device failure. no warranty is made with respect to uses, operati ng conditions, or combinations not represented on the data sheet. users considering application outs ide the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc , av cc 3.0 5.0 5.5 v under normal operation 2.6 ? 5.5 v maintains ram data in stop mode smoothing capacitor c s 0.1 ? 1.0 ? f use a ceramic capacitor or comparable capacitor of the ac characteristics. by- pass capacitor at the v cc pin should be greater than this capacitor. operating temperature t a ? 40 ? ? 105 c ? 40 ? ? 125 c * c c s ? c pin connection diagram
document number: 002-04578 rev. *a page 41 of 64 mb90910 series 11.3 dc characteristics (continued) parameter sym- bol pin name condition value unit remarks min typ max input ?h? voltage v ihs ?? 0.8 v cc ? v cc ? 0.3 v pin inputs if cmos hys- teresis input levels are selected v iha ?? 0.8 v cc ? v cc ? 0.3 v pin inputs if automotive input levels are selected v ihs p50, p82, p85 ? 0.7 v cc ? v cc ? 0.3 v pin inputs if cmos hys- teresis input levels are selected v ihr rst ? 0.8 v cc ? v cc ? 0.3 v rst input pin (cmos hysteresis) v ihm md0 to md2 ? v cc ? 0.3 ? v cc ? 0.3 v md input pin input ?l? voltage v ils ?? v ss ? 0.3 ? 0.2 v cc v pin inputs if cmos hys- teresis input levels are selected v ila ?? v ss ? 0.3 ? 0.5 v cc v pin inputs if automotive input levels are selected v ils p50, p82, p85 ? v ss ? 0.3 ? 0.3 v cc v pin inputs if cmos hys- teresis input levels are selected v ilr rst ? v ss ? 0.3 ? 0.2 v cc v rst input pin (cmos hysteresis) v ilm md0 to md2 ? v ss ? 0.3 ? v ss ? 0.3 v md input pin output ?h? voltage v oh other than p20 to p23 v cc ? 4.5 v, i oh ? ? 4.0 ma v cc ? 0.5 ?? v v ohi p20 to p23 v cc ? 4.5 v, i oh ? ? 14.0 ma v cc ? 0.5 ?? v mask rom products and evaluation products only output ?l? voltage v ol other than p20 to p23 v cc ? 4.5 v, i ol ? 4.0 ma ?? 0.4 v v oli p20 to p23 v cc ? 4.5 v, i ol ? 20.0 ma ?? 0.4 v mask rom products and evaluation products only input leak cur- rent i il ? v cc ? 5.5 v, v ss ? v i ? v cc ? 3 ? ? 3 ? a pull-up resistance r up p20 to p27, rst ? 25 50 100 k ? pull-down resistance r down md2 ? 25 50 100 k ? mask rom products and evaluation products only
document number: 002-04578 rev. *a page 42 of 64 mb90910 series (continued) * : the power supply current is measured with an external clock. parameter sym- bol pin name condition value unit remarks min typ max power supply current* i cc v cc v cc ? 5.0 v, internal frequency : 32 mhz, at normal operation. ? 30 40 ma v cc ? 5.0 v, internal frequency : 24 mhz, at normal operation. ? 22.5 30 ma v cc ? 5.0 v, internal frequency : 2 mhz, at normal operation. ? 37ma v cc ? 5.0 v, internal frequency : 32 mhz, at writing flash memory. ? 50 65 ma v cc ? 5.0 v, internal frequency : 32 mhz, at erasing flash memory. ? 50 65 ma i ccs v cc ? 5.0 v, internal frequency : 32 mhz, at sleep mode. ? 13 23 ma i cts v cc ? 5.0 v, internal frequency : 2 mhz, at main timer mode ? 0.3 0.9 ma i ctspll 8 v cc ? 5.0 v, internal frequency : 32 mhz, at pll timer mode, external frequency ? 4 mhz ? 47ma i cch v cc ? 5.0 v, at stop mode, t a ? ? 25 ? c ? 25 100 ? a input capacity c in other than av cc , av ss , avr, v cc , v ss , c ?? 515pf
document number: 002-04578 rev. *a page 43 of 64 mb90910 series 11.4 ac characteristics 11.4.1 clock timing parameter symbol pin name value unit remarks min typ max clock frequency f c x0, x1 3 ? 16 mhz 1/2 when pll stops, when using an oscillation circuit 4 ? 16 mhz pll ? 1, when using an oscillation circuit 4 ? 16 mhz pll ? 2, when using an oscillation circuit 4 ? 10 mhz pll ? 3, when using an oscillation circuit 4 ? 8mhz pll ? 4, when using an oscillation circuit 4 ? 5mhz pll ? 6, when using an oscillation circuit 4 ? 4mhz pll ? 8, when using an oscillation circuit clock cycle time t cyl x0, x1 62.5 ? 333 ns when using an oscillation circuit internal operating clock fre- quency (machine clock) f cp ? 1.5 ? 32 mhz when using main clock internal operating clock cy- cle time (machine clock) t cp ? 31.25 ? 666 ns when using main clock t cyl x0, x1 ? when using an oscillation circuit amplitude: it varies depending on the external resistance, power rating and the different kind of device. reference values: 1v to 2.5v note : the amplitude of mb90v950amas is the same as vcc.
document number: 002-04578 rev. *a page 44 of 64 mb90910 series guaranteed operation range of mb90910 series * : when using the oscillation circuit, the ma ximum oscillation clock frequency is 16 mhz. 5.5 3.5 4 1.5 32 4.0 gu a r a nteed oper a tion r a nge gu a r a nteed pll oper a tion r a nge intern a l clock f cp (mhz) power supply volt a ge v cc (v) ? guaranteed pll operation range 24 16 12 8 4.0 1.5 34 8 24 12 1/2 16 32 32 guaranteed oscillati on frequency range internal clock f cp external clock f c (mhz)* ? 4 ? 3 ? 2 (plloff) ? 6 ? 1 ? 8
document number: 002-04578 rev. *a page 45 of 64 mb90910 series 11.4.2 reset standby input * : oscillation time of oscillator is the time that the amplitude reaches 90 ? . in the crystal oscillator, the oscillation time is between several ms and tens of ms. in ceramic oscillators, the oscillation time is between hundreds of ? s and several ms. an external clock of oscillation time is 0 ms. parameter symbol pin name value unit remarks min max reset input time t rstl rst 500 ? ns under normal operation oscillation time of oscillator* ? 100 ? s ? ? s in stop mode 100 ? ? s in timebase timer mode rst x0 t rstl v ilr v ilr 100 s 90% of a mplitude instruction execution oscill a tion st ab iliz a tion w a iting time oscill a tion time of oscill a tor intern a l oper a tion clock intern a l reset rst v ilr t rstl v ilr ? under normal operation : ? in stop mode
document number: 002-04578 rev. *a page 46 of 64 mb90910 series 11.4.3 power-on reset note : if you change the power supply voltage too rapidly, a power -on reset may occur. we recommend that you start up smoothly by restraining voltages when changing the power supply voltage du ring operation, as shown in the figure below. perform while not using the pll clock. however, if voltage drops are within 1 v/s, you can operate while using the pll clock. 11.4.4 uart escr : sces = 0, eccr : scde = 0 *: the tcp indicates machine clock parameter symbol pin name condition value unit remarks min max power on rise time t r v cc ? 0.05 30 ms power off time t off v cc 1 ? ms due to repetitive operation parameter symbol condition value unit min max serial clock cycle time t scyc internal shift clock operation c l = 80pf + 1ttl. 5 tcp* ? ns sck ? ? sot delay time t slovi ? 50 ? 50 ns sin ? sck ? setup time t ivshi tcp ? 80 ? ns sck ? ? sin hold time t shixi 0 ? ns serial clock ?l? pulse width t slsh external shift clock operation c l = 80pf + 1ttl. 3 tcp ? t r ? ns serial clock ?h? pulse width t shsl tcp ? 10 ? ns sck ? ? sot delay time t slove ? 2 tcp ? 60 ns sin ? sck ? setup time t ivshe 30 ? ns sck ? ? sin hold time t shixe tcp ? 30 ? ns sck fall time t f ? 10 ns sck rise time t r ? 10 ns v cc t r t off 2.7 v 0.2 v 0.2 v 0.2 v v cc v ss 3 v hold s ram data we recommend a ri s e of 50 mv/m s maxim u m.
document number: 002-04578 rev. *a page 47 of 64 mb90910 series sck sot sin v il v ih t shixi t slovi 2.4 v 0.8 v 2.4 v 0.8 v t scyc t ivshi internal clock shift operation sck sot sin t slsh t shsl t f t r t slove t ivshe t shixe v ih v il v ih v il 2.4 v 0.8 v external clock shift operation
document number: 002-04578 rev. *a page 48 of 64 mb90910 series escr : sces = 1, eccr : scde = 0 *: the tcp indicates machine clock parameter symbol condition value unit min max serial clock cycle time t scyc internal shift clock opera- tion c l = 80pf + 1ttl. 5 tcp* ? ns sck ? ? sot delay time t shovi ? 50 ? 50 ns sin ? sck ? setup time t ivsli tcp ? 80 ? ns sck ? ? sin hold time t slixi 0 ? ns serial clock ?h? pulse width t shsl external shift clock opera- tion c l = 80pf + 1ttl. 3 tcp ? t r ? ns serial clock ?l? pulse width t slsh tcp ? 10 ? ns sck ? ? sot delay time t shove ? 2 tcp ? 60 ns sin ? sck ? setup time t ivsle 30 ? ns sck ? ? sin hold time t slixe tcp ? 30 ? ns sck fall time t f ? 10 ns sck rise time t r ? 10 ns sck sot sin t shovi t ivsli t slixi 2.4 v 0.8 v v ih v il 2.4 v 0.8 v t scyc internal clock shift operation
document number: 002-04578 rev. *a page 49 of 64 mb90910 series sck sot sin t shsl t slsh t r t f t shove t ivsle t slixe v ih v il v ih v il 2.4 v 0.8 v external clock shift operation
document number: 002-04578 rev. *a page 50 of 64 mb90910 series escr : sces = 0, eccr : scde = 1 *: the tcp indicates machine clock parameter symbol condition value unit min max serial clock cycle time t scyc internal shift clock opera- tion c l = 80pf + 1ttl. 5 tcp* ? ns sck ? ? sot delay time t shovi ? 50 ? 50 ns sin ? sck ? setup time t ivsli tcp ? 80 ? ns sck ? ? sin hold time t slixi 0 ? ns sot ? sck ? delay time t sovli 3 tcp ? 70 ? ns sck sot sin t scyc t sovli t ivsli t slixi v ih v il v ih v il 2.4 v 0.8 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v t shovi
document number: 002-04578 rev. *a page 51 of 64 mb90910 series escr : sces = 1, eccr : scde = 1 *: the tcp indicates machine clock 11.4.5 trigger input timing note : t cp is internal operating clock cycle time (mach ine clock) . refer to ? (1) clock timing?. parameter symbol condition value unit min max serial clock cycle time t scyc internal clock operation c l = 80pf + 1ttl. 5 tcp* ? ns sck ? ? sot delay time t slovi ? 50 ? 50 ns sin ? sck ? setup time t ivshi tcp ? 80 ? ns sck ? ? sin hold time t shixi 0 ? ns sot ? sck ? delay time t sovhi 3 tcp ? 70 ? ns parameter symbol pin name condition value unit min max input pulse width t trgh t trgl int8, int9r int10, int11 int12r, int13 int14r, int15r adtg ? 5 t cp ? ns sck sot sin t scyc t sovhi t ivshi t shixi t slovi v ih v il v ih v il 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v v il v ih t trgh v il v ih t trgl int 8 , int9r int10, int11 int12r, int1 3 int14r, int15r adtg
document number: 002-04578 rev. *a page 52 of 64 mb90910 series 11.4.6 timer related resource input timing note : t cp is internal operating clock cycle time (mach ine clock) . refer to ? (1) clock timing?. 11.4.7 timer related resource output timing parameter symbol pin name condition value unit min max input pulse width t tiwh tin2, tin3 in0 to in3 ? 4 t cp ? ns t tiwl parameter symbol pin name condition value unit min max clk ? ? t out change time t to tot2, tot3 ppga to ppgf ? 30 ? ns v il v ih t tiwh v il v ih t tiwl tin2, tin 3 in0 to in 3 clk 2.4 v 0.8 v 2.4 v t to tot2, tot3 ppga to ppgf
document number: 002-04578 rev. *a page 53 of 64 mb90910 series 11.4.8 can pll cycle jitter parameter sym- bol pin name condition value unit remarks min typ max can pll cycle jitter (when locked) t pj ?? ? 10 ? ? 10 ns f cp ? 16 mhz (4 mhz multiplied by 4) 24 mhz (4 mhz multiplied by 6) 32 mhz (4 mhz multiplied by 8) t1 t2 t3 t1 t2 t3 tn-1 tn tn-1 tn ? can pll cycle jitter deviation time from the ideal clock is assured per cycle out of 20, 000 cycles. pll output ideal clock deviation time slow fast
document number: 002-04578 rev. *a page 54 of 64 mb90910 series 11.5 a/d converter (3.0 v ? avr ? av ss ) * : if a/d converter is not operating, a current when cpu is stopped is applicable (v cc ? av cc ? avr ? 5.0 v) . parameter symbol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? ? 3.0 lsb nonlinearity error ?? ? ? ? 2.5 lsb differential nonlinearity error ?? ? ? ? 1.9 lsb zero reading voltage v ot an0 to an15 av ss ? 1.5lsb av ss ? 0.5lsb av ss ? 2.5lsb v full scale reading voltage v fst an0 to an15 avr ? 3.5lsb avr ? 1.5lsb avr ? 0.5lsb v compare time ?? 0.66 ? 16500 ? s 4.5 v ? av cc ? 5.5 v 2.2 3.0 v ? av cc < 4.5 v sampling time ?? 0.4 ? ?? s 4.5 v ? av cc ? 5.5 v 1.0 3.0 v ? av cc < 4.5 v analog port input current i ain an0 to an15 ? 3 ? ? 3 ? a analog input voltage range v ain an0 to an15 av ss ? avr v reference voltage range ? avr av ss ? 2.7 ? av cc v power supply current i a av cc ? 3.5 7.5 ma i ah av cc ?? 5 ? a* reference voltage supply current i r avr ? 600 900 ? a i rh avr ?? 5 ? a* offset between input channels ? an0 to an15 ?? 4lsb
document number: 002-04578 rev. *a page 55 of 64 mb90910 series ? about the external impedance of analog input and its sampling time a/d converter with sample and hold circuit. if the external impedance is too high to keep sufficient sampling time, the analog voltage changed to the internal sample and hold capacitor is insuffici ent, adversely affecting a/d conver sion precision. therefore, to satisfy the a/d conversion precision standard, cons ider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decre ase the external impedance so that the sampling time is longer than the minimum value. and, if the sampling time can not be sufficient, connect a capacitor of about 0.1 ? f to the analog input pin. c r ? analog input equivalent circuit model analog input note : the values are reference values. 4.5 v ? av cc ? 5.5 v : r : = 2.52 k ? , c : = 10.7 pf 4.0 v ? av cc < 4.5 v : r : = 13.6 k ? , c : = 10.7 pf 4.5 v ? av cc ? 5.5 v : r : = 4.1 k ? , c : = 8.5 pf 4.0 v ? av cc < 4.5 v : r : = 10.33 k ? , c : = 8.5 pf mb90v950amas mb90f912bs mb90911as comparator
document number: 002-04578 rev. *a page 56 of 64 mb90910 series 11.6 definition of a/d converter terms (continued) resolution : analog variation that is recognized by an a/d converter. non linearity error : deviation between a line across zero-transition line ( ?00 0000 0000 b ? ? ? ?00 0000 0001 b ? ) and full-scale transition line ( ?11 1111 1110 b ? ? ? ?11 1111 1111 b ? ) and actual conver sion characteristics. differential linearity error : deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. total error : difference between an actual value and an theoretical value. a total error includes zero transition error, full-scale transition error, and linear error. 3 ff h 3 fe h 3 fd h 004 h 00 3 h 002 h 001 h av ss avr v nt 1.5 l s b 0.5 l s b {1 l s b (n ? 1) + 0.5 l s b} act u al conver s ion characteri s tic s (act u ally-mea su red val u e) act u al conver s ion characteri s tic s ideal characteri s tic s digital o u tp u t analog inp u t total error total error of digital output ?n? ? v nt ? {1 lsb ? (n ? 1) ? 0.5 lsb} 1 lsb [lsb] 1 lsb (ideal value) ? avr ? av ss 1024 [v] v ot (ideal value) ? av ss ? 0.5 lsb [v] v fst (ideal value) ? avr ? 1.5 lsb [v] v nt : a voltage at which digital output transits from (n ? 1) h to n h . n : a/d converter digital output value
document number: 002-04578 rev. *a page 57 of 64 mb90910 series (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avr av ss avr n + 1 n n ? 1 n ? 2 v ot ( a ctu a l me a surement v a lue ) { 1 lsb (n ? 1) + v ot } actu a l conversion ch a r a cteristics v fst ( a ctu a l me a surement v a lue) v nt ( a ctu a l me a surement v a lue) actu a l conversion ch a r a cteristics ide a l ch a r a cteristics actu a l conversion ch a r a cteristics actu a l conversion ch a r a cteristics ide a l ch a r a cteristics digit a l output digit a l output an a log input an a log input v nt ( a ctu a l me a surement v a lue) v (n + 1) t ( a ctu a l me a surement v a lue) non linearity error diffe rential linearity error non linearity error of digital output n ? v nt ? {1 lsb ? (n ? 1) ? v ot } 1 lsb [lsb] differential linearity error of digital output n ? v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] 1 lsb ? n : a/d converter digital output value v ot : voltage at which digital output transits from ?000 h ? to ?001 h .? v fst : voltage at which digital output transits from ?3fe h ? to ?3ff h .?
document number: 002-04578 rev. *a page 58 of 64 mb90910 series ? about errors as | avr ? av ss | becomes smaller, values of relative errors grow larger. ? at 4.5 v ? av cc ? 5.5 v minimum sampling time [ ? s] (external impedance ? 0 k ? to 20 k ? ) ? at 3.0 v ? av cc < 4.5 v (external impedance ? 0 k ? to 100 k ? ) (external impedance ? 0 k ? to 20 k ? ) ? the relationship between external impedance and minimum sampling time external impedance [k ? ] (external impedance ? 0 k ? to 100 k ? ) minimum sampling time [ ? s] external impedance [k ? ] minimum sampling time [ ? s] external impedance [k ? ] minimum sampling time [ ? s] external impedance [k ? ] mb90911as mb90f912bs 100 90 80 70 60 50 40 30 20 10 0 0 510 1 2 34 67 8 9 mb90v950amas mb90911as mb90f912bs 20 18 16 14 12 10 8 6 4 2 0 0 5 1 2 3 4 mb90v950amas mb90911as mb90f912bs 100 90 80 70 60 50 40 30 20 10 0 0 510 1 2 34 67 8 9 mb90v950amas mb90911as mb90f912bs 20 18 16 14 12 10 8 6 4 2 0 0 5 1 2 3 4 mb90v950amas minimum sampling time [ ? s](4.5 v ? avcc ? 5.5 v) external impedance [k ? ] 5 10 50 mb90911as/mb90f912bs 0.54 0.84 3.22 mb90v950amas 0.56 0.94 3.93 minimum sampling time [ ? s] (3.0 v ? avcc ? 4.5 v) external impedance [k ? ] 5 10 50 mb90911as/mb90f912bs 0.91 1.21 3.59 mb90v950amas 1.39 1.77 4.76
document number: 002-04578 rev. *a page 59 of 64 mb90910 series 11.7 flash memory program/erase characteristics * : corresponding value comes from the technology reliability eval uation result (using arrhenius equation to translate high temp erature measurements into normalized value at +85 c ) . parameter conditions value unit remarks min typ max sector erase time t a ? ? 25 c v cc ? 5.0 v ? 0.9 3.6 s excludes programming prior to erasure chip erase time ? 5.4 21.6 s byte (8-bit width) programming time ? 15 240 ? s except for the overhead time of the system level word (16-bit width) programming time ? 23 370 ? s program/erase cycle t a ? ? 85 c 10000 ?? cycle t a ? ? 85 c 100000 ?? cycle flash memory data retention time average t a ? ? 85 c 20 ?? year *
document number: 002-04578 rev. *a page 60 of 64 mb90910 series 12. ordering information part number package remarks MB90F912BSPMC 48-pin plastic lqfp (fpt-48p-m26) mb90911aspmc mb90v950amascr-es 299-pin ceramic pga (pga-299c-a01) for evaluation
document number: 002-04578 rev. *a page 61 of 64 mb90910 series 13. package dimension 48-pin pl a stic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 7 7 mm le a d sh a pe gullwing se a ling method pl a stic mold mounting height 1.70 mm max weight 0.17 g code (reference) p-lfqfp48-7 7-0.50 48-pin pl a stic lqfp (fpt-48p-m26) (fpt-48p-m26) c 2003 fujitsu limited f48040s-c-2-2 24 13 36 25 48 37 index sq 9.00?.20(.354?008)sq 0.145?.055 (.006?002) 0.08(.003) "a" 0?~8? .059 ?004 +.008 ?.10 +0.20 1.50 0.60?.15 (.024?006) 0.10?.10 (.004?004) (st a nd off) 0.25(.010) det a ils of "a" p a rt 1 12 0.08(.003) m (.008?002) 0.20?.05 0.50(.020) lead no. (mounting height) .276 ?004 +.016 ?.10 +0.40 7.00 * dimensions in mm (inches). note: the v a lues in p a rentheses a re reference v a lues. ?003-2008 fujitsu microelectronics limited f48040s-c-2-3 note 1) * : these dimensions include resin protrusion. note 2) pins width a nd pins thickness include pl a ting thickness. note 3) pins width do not include tie ba r cutting rem a inder.
document number: 002-04578 rev. *a page 62 of 64 mb90910 series 14. major changes (continued) section change results ? changed the part number. mb90f912as ? mb90f912bs mb90v950mas ? mb90v950amas product lineup mb90v950amas corrected the adapter boad. mb2147-20 rev.04c ? mb2147-20 rev.04c or later pin description pin no.18,pin no.19, pin no.33 to pin no.35,pin no.36 added the function as follows for pi ns p56, p57, p23 to p21, p20. (different i/o circuit type from mb90v950amas). i/o circuit types typec,typed added to the ?evaluation product? on remarks. typek corrected the circuit. cmos input ? cmos hysteresis input typel handling devices added the item as follows. 3.using external clock block diagrams mb90v950amas corrected for the prescaler. 5 channels ? 7 channels electrical characteristics dc characteristics input ?h? voltage corrected the pin v ihs . ? ? ? ? p50, p82, p85 corrected the pin v ihr . ? ? ? ? rst corrected the pin v ihm . ? ? ? ? md0 to md2 input ?l? voltage corrected the pin v ils . ? ? ? ? p50,p82,p85 corrected the pin v ilr . ? ? ? ? rst corrected the pin v ilm . ? ? ? ? md0 to md2 output ?h? voltage added to remarks of v ohi . mask rom products and evaluation products only output ?l? voltage added to remarks of v ol . mask rom products and evaluation products only input leak current corrected the value. min : ? 1 ? ? 3 max : ? 1 ? ? 3 pull-down resistance corrected the remark. mask rom products only ? mask rom products and evaluation products only ac characteristics reset standby input changed the unit for ?oscillati on time of oscillator*+ 100 ? s? . ns ? ? s can pll cycle jitter added the item.
document number: 002-04578 rev. *a page 63 of 64 mb90910 series (continued) note: please see ?document history? about later revised information. document history section change results a/d converter corrected the remark of ?compare time?. 4.5 v ? av cc ? 4.5 v ? av cc ? 5.5 v 3.0 v ? av cc ? 3.0 v ? av cc < 4.5 v corrected the remark of ?sampling time?. 4.5 v ? av cc ? 4.5 v ? av cc ? 5.5 v 3.0 v ? av cc ? 3.0 v ? av cc < 4.5 v changed the value of ?analog port input current ?. min : ? 0.3 ? ? 3 max : ? 0.3 ? ? 3 ordering information changed the part number. mb90f912aspmc ? MB90F912BSPMC mb90v950mascr-es ? mb90v950amascr-es document title: mb90911as/f912bs/v950amas f 2 mc-16lx mb90910 series 16-bit microcontroller document number: 002-04578 revision ecn orig. of change submission date description of change ** ? akih 06/04/2009 migrated to cypress and assigned document number 002-04578. no change to document contents or format. *a 5218093 taoa 04/12/2016 updated to cypress template
document number: 002-04578 rev. *a revised april 12, 2016 page 64 of 64 mb90910 series ? cypress semiconductor corporation, 2008-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a crit ical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trad emarks of cypress in the united states and other countries. for a more complete list of cypre ss trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions cypress.com/psoc psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/support

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